The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to the structure and simultaneous formation of through-substrate-vias (TSV) with self-aligned solder bumps.
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilayered schemes, such as, for example, single or dual damascene wiring structures. A TSV is a vertical electrical connection (via) passing completely through a substrate such as a silicon wafer or die. TSVs are high performance interconnect techniques used as to carry signals through a substrate and to mitigate the effect of chip modes and prevent the appearance of slot-line modes. TSVs can be used to create 3D packages and 3D integrated circuits, compared to alternatives such as package-on-package, because the density of the vias is substantially higher, and because the length of the connections is shorter. Bump bonds generally begin as small spheres of solder that are bonded to contact areas or pads of semiconductor devices. Subsequently, the bump bonds are used for face-down bonding such as can occur in flip chip applications, which are also known as controlled collapse chip connection (C4). The bumps can then be reflowed to complete the interconnect. The bump serves to both mechanically attach the two chips as well as form an electrical connection between elements on both chips, or between grounded portions of the circuitry.